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Index

$D600-$D601

54784 $D600 VDCADR

Address/status register

The VDC actually has two different registers at this location: a write-only address register and a read-only status register. Any value you store in this location goes to the address register.

The value specifies which one of the 37 internal VDC registers can be accessed via the data register at 54785/$D601. Since only six bits are needed to specify all the valid register numbers (0-36), bits 6 and 7 of the address register are unused and have no effect when you are writing to this register.

You can’t read this location to determine which internal register is being accessed; reading always returns the status register contents. The status register bits are defined as follows:

Bits 0-2: these locations hold a constant number (like a ROM location) indicating the version number of the VDC chip currently installed. There have been two versions of the VDC to date. In early 128s, the value here will be %000 = 0, while in later models the value will be %001 = 1, The exact difference between the versions is not clear, but they do require slightly different initialization. Specifically, internal register 25, the horizontal smooth scrolling register, requires different settings for the different versions. The IOINIT routine $E109 checks these VDC status register bits and performs the initialization accordingly.

Bits 3-4: these bits are unused, and always return %0 when read.

Bit 5: This bit, called the VBLANK flag, is used to indicate when the VDC raster scan is in its vertical blank period. After a full screen has been drawn and the electron beam has reached the lower right corner of the display, the beam must be turned off briefly while it is moved back to its home position in the upper left corner to begin the next frame. Otherwise, moving the beam would result in a diagonal line across the screen. The time while the beam is turned off for this repositioning is called the vertical blanking interval.

This bit, normally %0, will be set to %1 during the vertical blanking period. When you’re programming special screen effects, it’s handy to know when the blanking period is occurring. The time when one frame has been completely drawn but another one has not yet been started is a good time to change screen parameters without causing excessive flicker. The VIC chip can generate a raster interrupt to signal when its vertical blanking interval is beginning, but the VDC chip can’t generate interrupt requests, so this bit provides an alternate method of signaling that vertical blanking is in progress.

Bit 6: This bit, known as the LP flag, is used to indicate when new values have been latched in the internal light pen registers. Whenever a pulse is detected on the VDC chip’s LP input line, the row and column positions of the raster beam at that time are latched into internal registers 16-17/$10-$11 and this bit is set to %1. This bit will remain %1 until one or both of the internal light pen registers are read, at which time it will be reset to %0.

Thus, a %1 in this bit is a signal that a new light pen position can be read from the internal registers, while a %0 indicates that the register values have not changed since they were last read. See the entry for internal registers 16-17/$10-$11 for details of light pen reading.

Bit 7: This bit, known as the STATUS flag, is used to indicate that the VDC is ready to read from or write to the internal register specified by writing to the external address register. The flag bit will be set to %0 when a value is stored in this Io cation, and will return to %1 whe n the specified register is ready for access. The standard procedure for reading from or writing to a VDC register is as follows.

Writing:

    ldx #register number
    stx $D600
  Wait:
    ldx $D600
    bpl Wait
    lda $D601

Reading:

    ldx #register number
    stx $D600
  Wait:
    ldx $D600
    bpl Wait
    sta $D601

Refer to the entry below for information concerning the restrictions on accessing this location from BASIC.

54786 $D601 VDCDAT

Data register

This register is the gateway to the internal registers of the VDC. After you have set the desired internal register number by writing to the address register at 54784/$D600, the specified register becomes visible at this location.

Reading from this location shows the internal register contents, and writing to this location stores the value in the internal register. Once you specify an internal register, that register remains visible here until you change registers by storing a new value in 54784/ $D600. Refer to the internal register descriptions below for more information on the effects of reading from and writing to the various registers.

Commodore’s specifications for this chip state that when accessing the VDC, you should avoid machine language instructions that use the indirect addressing mode. That is, you should avoid using instructions like LDA ($CC),Y to read this register because the VDC apparently responds improperly to such instructions. This imposes no particular hardship on machine language programmers, but has highly unfortunate consequences for BASIC programmers.

The 128’s PEEK, POKE, and WAIT instructions are implemented using the Kernal INDFET, INDSTA, and INDCMP routines, all of which use indirect-Y addressing to read or store values. As a result, you should not use PEEK, POKE, or WAIT statements to read or change the contents of this location or of location 54784/$D600.

This would seem to make the VDC inaccessible from BASIC. Fortunately, a pair of screen editor ROM routines provide a simple detour around this roadblock. They are designated WRITEREG $CDCC and READREG $CDDA, and they have the form shown above in the discussion of location 54784/$D600. To store a value in any VDC register from BASIC, use:

SYS DEC("CDCC"), value, register

or

SYS 52684, value, register

where register is the number (0-36) of the internal VDC register you wish to access, and value is the value (0-255) you wish to place in that register. If you have used any other BANK statements in your program, it would be wise to add a BANK 15 statement before these SYS statements to insure the proper memory configuration. To read the contents of an internal VDC register from BASIC, use a statement of the form:

SYS DEC("CDDA"),, register : RREG A

or

SYS 52698,, register : RREG A

Be sure you have two commas between the SYS address and the register number. After this statement has been executed, the variable A will contain the value read from the specified register. Again, if you change bank configurations elsewhere in your program, it would be wise to add a BANK 15 before the SYS statement.

See also