These registers are used to read data from port lines which are configured as inputs and to write data to port lines configured as outputs. Refer to the entry for the CIA #1 ports at $DC00-$DC01 for details of how these registers and ports operate. For CIA #2, the ports are used as follows:
Bits 0-1 of this port (lines FA0-PA1) are normally configured as outputs and are used to specify which 16K area of the 64K RAM block will be used for the current VIC video bank. The four possible selections are as follows:
| Bits 1 0 | Video bank | System address range |
|---|---|---|
| 0 0 | 3 | 49152-65535/$C000-$FFFF |
| 0 1 | 2 | 32768-49252/$8000-$BFFF |
| 1 0 | 1 | 16384-32767/$4000-$7FFF |
| 1 1 | 0 | 0-16383/$0000-$3FFF |
These bits are initialized to %11 by the IOINIT routine $E109 during the reset and RUN/STOP-RESTORE sequences. This selects video bank 0, the default bank, and the 128 itself never selects another bank. The 64K block from which the video bank is seen is determined by bit 6 of the MMU register at $D506.
Bit 2 (port line PA2) is connected to pin M of the user port. The line is normally configured as an output, and this bit is initialized by the IOINIT routine to %1, allowing the line to go high (+5 volts). The Kernal RS-232 routines use this line as the transmitted data (TXD) output. You can also use the user port line for your own I/O functions.
The remaining bits are used for the serial bus, the 128’s avenue of communications with disk drives and printers. The lines are connected as follows:
| Bit | Port line | Function |
|---|---|---|
| 3 | PA3 | Handles output on the serial bus ATN line |
| 4 | PA4 | Handles output on the serial bus CLK line |
| 5 | PA5 | Handles output on the serial bus DATA line (for slow serial mode) |
| 6 | PA6 | Handles input from the serial bus CLK line |
| 7 | PA7 | Handles input from the serial bus DATA line (for slow serial mode) |
The bits for the output lines are all initialized to %0 by the IOINIT routine, causing the output lines to be pulled low (0 volts). However, all these lines have inverters between the CIA and the serial port connector, so pulling the port lines low allows the lines at the serial port connector to go high. Refer to the discussion of Kernal serial input and output routines in Chapter 9 for more information on how these lines are used for serial bus communications.
All the lines from port B are tied directly to the user port, a 24-pin connector located on the back of the 128. The lines are connected as follows:
| Bit | Port B line | User port pin |
|---|---|---|
| 0 | PB0 | C |
| 1 | PB1 | D |
| 2 | PB2 | E |
| 3 | PB3 | F |
| 4 | PB4 | H |
| 5 | PB5 | J |
| 6 | PB6 | K |
| 7 | PB7 | L |
All port lines are initialized as inputs, but this can be changed by changing the value in the port’s data direction register at 56579/$DD03. The handshake line (PC) for port B is also available at pin 8 of the user port, These lines provide a full eight-bit parallel I/O port for your own interfacing projects. However, the port B lines also have another use. The 128 lacks a true RS-232 hardware interface, so the Kernal RS-232 routines program the user port lines to support RS-232 communications. For RS-232, the port lines are used as follows:
| Bit | Line | Pin | RS-232 function |
|---|---|---|---|
| 0 | FLAG | B | This interrupt input is tied to the received data line. The high-to-low transition on the line at the beginning of the start bit for an incoming byte will cause a FLAG interrupt to initiate the reception of the byte |
| PB0 | C | RXD (received data). This input line is used to read incoming data bits from the modem or other external device | |
| PB1 | D | RTS (request to send). This output line is used to signal the modem that the 128 is ready to send a byte | |
| 1 | PB2 | E | DTR (data terminal ready). This output line is used to signal the modem that the 128 RS-232 interface is active |
| 3 | PB3 | F | RI (ring indicator). This input line is not supported by the Kernal RS-232 routines, but is intended to allow the modem to signal the 128 that a ringing signal has been detected on the phone line. The line, normally high, goes low when a ring is detected. (Commodore modems support this line.) |
| 4 | PB4 | H | DCD (carrier detected). This input line is used to allow the modem to signal the 128 that it has detected another modem on the other end of the telecommunications link. The line, normally high, goes low when the incoming carrier signal is detected |
| 5 | PBS | J | This line is not formally assigned, but Commodore modems use it to control whether or the not the modem is connected to the phone line. Since the line is configured by the IOINIT routine as an input, you must change the corresponding data direction register bit to %1 to use the line as an output for this control function. Writing a %0 to this bit will connect the modem to the phone line (the off-hook state), while writing a %1 will disconnect (hang up) the modem |
| 6 | PB6 | K | CT5 (clear to send). This input line is used to allow the modem to signal the 128 that it is ready to accept another byte |
| 7 | PB7 | L | DSR (data set ready). This input line is used to allow the modem to signal the 128 that it is active |
| PA2 | M | The following port A line is also used: TXD (transmitted data). This output line is used to send data bits to the modem or external device |
These registers specify whether the lines of ports A and B will be inputs or outputs. Refer to the discussion of the CIA #1 data direction registers at $DC02-$DC03 for details of how these registers operate. For CIA #2, the IOINIT routine $E109-part of both the reset and RUN/STOP-RESTORE sequences- initializes the port A DDR (56578/$DD02) to 63/$3F, making port A lines PA0-PA5 outputs and lines PA6-PA7 inputs, and the port B DDR (56579/$DD03) to 0/$00, making all port B lines inputs. The port A setting is not changed by any other ROM routine. Bits 0-1 of the port A register should always remain set to %1 to keep PA0-PA1 outputs for the VIC video bank selection function. You can change the setting of the port B register freely to achieve the desired user port I/O configuration. The routine to set up CIA #2 for R5-232 communications $F0B0 will set the port B DDR to 6/$06, which changes lines PB1-PB2 to outputs and all the others to inputs. See the discussion of the data registers at $DD00-$DD01 for more information on the uses of the port lines.
Refer to the discussion of CIA #1 timer A at $DC04-$DC05 for details of how these registers operate. For CIA #2, the latch value for the timer is not specifically initialized during the reset or RUN/STOP-RESTORE sequences, although resetting the system will automatically set the latch count to 65535/$FFFF. The only use for this timer in system ROM is during the routines which transmit bits over the RS232 interface, where it is used to determine the duration of outgoing bits. After RS-232 transmission is completed, the timer will continue running with a latch count value dependent on the baud rate used in the RS-232 communications.
Refer to the discussion of CIA #1 timer B at $DC06-$DC07 for details of how these registers operate. For CIA #2, the latch value for the register is not specifically initialized during the reset or RUN/STOP-RESTORE sequences, although resetting the system will automatically set the latch count to 65535/$FFFF. The only use for this timer in system ROM is during the routines which receive bits from the RS232 interface, where it is used to determine the duration of incoming bits. After RS-232 reception is completed, the timer will continue running with a latch count value dependent on the baud rate used in the RS-232 communications.
###Time-of-day clock registers Refer to the discussion of the CIA #1 time-of-day clock registers at $DC08-$DC0B for details of how these registers operate. Like the CIA #1 time-of-day clock, these registers are unused in 128 mode, and are available for your own timekeeping projects.
Refer to the discussion of the CIA #1 serial data register at $DC0C for details of how this register operates. Unlike the serial data line from CIA #1, the serial port (SP) line from CIA #2 is not used by the 128. It is, however, available at pin 7 of the user port on the back of the 128, along with the CNT Une (at pin 6), so you can use this port for your own interfacing projects.
Refer to the discussion of the CIA #1 interrupt control register at $DC0D for details of how this register operates. Because of the way CIA #2 is wired into the 128 system, the interrupts it generates trigger processor NMI interrupts instead of the IRQ interrupts generated by CIA #1. The IOINIT routine $E109, executed during both the reset and RUN/ STOP-RESTORE sequences, initializes the interrupt mask for this register to 0/$00, disabling all interrupt sources. Any CIA #2 interrupt source can trigger an NMI interrupt, but 128 ROM routines use only three of the possible sources: NMI interrupts generated by FLAG, timer A, and timer B are used to drive RS-232 communications. You can use any CIA #2 source to generate an NMI interrupt for your own purposes. (The FLAG interrupt input line is available at pin B of the user port.) However, you’ll have to write your own interrupt handling routine. The standard NMI handler $FA40 assumes that any CIA #2-generated interrupt it encounters is for RS-232.
Refer to the discussions of CIA #1 control registers A and B at $DC0E and $DC0F, respectively, for details of how these registers operate. For CIA #2, these registers are both initialized to 8/$08 by the IOINIT routine $E109, part of both the reset and RUN/STOP-RESTORE sequences. This value leaves both rimers stopped and set for one-shot mode. The only ROM routines which change those settings are the Kernal’s RS-232 I/O routines. Timers A and B are used to generate the NMI interrupts which drive the transmission and reception of bits over the RS-232 interface. When RS-232 transmission is started, timer A is started, and it will continue running in continuous mode even after the transmission is completed and the logical file for RS-232 is closed ($DD0E will be set to 1/$01). Likewise, timer B is started when the first RS-232 byte is received, and will continue running in continuous mode even after the reception is complete and the logical file has been dosed ($DD0F will be set to 1/$01).
Due to incomplete address decoding, images of the CIA chip registers appear repeatedly every 16 bytes throughout the remainder of this page of memory. That is, storing a value in any location in this range with an address that is an exact multiple of 16 greater than one of the base register addresses has the same effect as storing the same value in one of the base register locations. For example, storing a value in $DD10 or $DDF0 has the same effect as storing a value in $DD00. However, it’s better programming practice to use the officially designated register addresses.